The stack-gate ETOX cell, one of the most popular cell structures for flash memories, is widely programmed by channel hot-electron (CHE) and erased by Fowler-Nordheim (FN) tunneling through the source side or the channel area.
The n-channel ETOX cell is conventionally fabricated by a twin-well process or recently in a triple-well process as shown in FIG. 1. The triple-well structure is typically used to protect cells from noises generated outside the deep n-well by reverse-biasing the deep n-well to p-well junction, e.g., the deep n-well is biased to the positive power supply (Vcc) and the p-well is biased to ground (Vss). The n+source is typically doubly implanted by As.sup.75 (with a high dose of .about.1E16/cm.sup.2) and P.sup.31 (with a lower dose of .about.1E14/cm.sup.2) so that the source junction is a graded junction and can be biased at high voltage (e.g. .about.12 v) during erase operation. The n+ drain is typically implanted by As only with a high dose (.about.1E16/cm.sup.2) and the drain side does not need the lightly-doped-drain (LDD) implant and spacer structure.
Note that the LDD structure is not useful in an ETOX cell, although it is important in normal CMOS transistors for reducing electrical field during switching for lower hot-electron generation. The tunnel oxide (T.sub.ox) is typically 80-120 angstroms thick, the inter-poly dielectric (T.sub.pp) typically consists of thin nitride-oxide (ONO) layers. As an example, a typical ETOX cell based on a 0.35 um CMOS design rule has the following cell parameters: T.sub.ox .about.90 angstroms, T.sub.pp .about.160 angstroms (oxide equivalent thickness), and control-gate to floating-gate coupling ratio of .about.0.8.
The ETOX cell of FIG. 1 is typically programmed by channel-hot-electrons (CHE). Notations for biases at all nodes are defined in FIG. 1. The bias for programming is typically: V.sub.d .about.7 v, V.sub.cg .about.+9 to +12 v, and V.sub.s =0 v. Under these bias conditions, there is a large channel current (.about.1 mA/cell) for hot electron generation near the channel surface of the drain. Hot electrons are injected into the floating-gate when the oxide energy barrier is overcome and when assisted by the positive control gate bias. After programming, the amount of net electrons on the floating-gate increases, which results in an increase of the cell threshold voltage (V.sub.T). The electrons in the floating-gate will remain for a long time (e.g. 10 years at room temperature), unless intentionally erased. The drawback of CHE programming is low injection efficiency and large power consumption during programming.
The cell is typically erased by Fowler-Nordheim (F-N) tunneling through the source side or the channel area. The bias during source side erase is typically: V.sub.d .about.0 v or floating, V.sub.cg .about.-5 v to 0 v, and V.sub.s =+9 to +12 v. This establishes a large electrical field (.about.10 Mv/cm) across the tunnel oxide between the floating-gate and source overlap area. Electrons on the floating-gate will tunnel into the source and be removed away. It is known that there is large gate induced drain leakage (GIDL) current that occurs at the source side during erase as well as the associated degradation of the tunnel oxide.
The bias for F-N erase through the channel area is typically: V.sub.d .about.floating, V.sub.cg .about.15 v, V.sub.pw .about.0 v. A large electrical field (-10 Mv/cm) can be established across the tunnel oxide between the floating-gate and the p-well channel area (in accumulation). Electrons on the floating-gate will tunnel into the channel area and be removed through the p-well bias. It is well known that a high negative voltage is required on the control-gate and the tunnel oxide is easily degraded by the high field during erase.
The bias for read operation of prior art ETOX cell is typically: V.sub.d .about.1 v to 2 v, V.sub.cg .about.V.sub.cc, V.sub.s .about.0 v, V.sub.pw .about.0 v, V.sub.dnw =V.sub.cc, and V.sub.sub .about.0 v. V.sub.cc is 3.3 v for 0.35 micron CMOS technology, and is 2.5 v for 0.25 micron CMOS technology. The channel may be inverted or not depending on the net electron charge stored on the floating-gate, and results in the on and off of the cell as measured by the read current I.sub.read representing the digital information of "1" or "0" stored in the cell.
A conventional NOR array is shown in FIG. 2, where the nodes of each ETOX cell can be accessed randomly. The drain of an ETOX cell is connected to a column (bit-line) through a contact and metal line. The control gate of the ETOX cell is connected to a row (word-line). The source of adjacent ETOX cells are connected together by n+diffusion regions (row) and is shared by an adjacent row. The source line of the entire array is shorted together through additional metal lines.
The entire array is formed in a large p-well biased at V.sub.ss if fabricated with a triple-well front end. Notice that the potential of a column is high (e.g., Vcc) if all word-lines are biased low (i.e., all cells in a column are not selected and not turned "on"). This is similar to the NOR logic function with the column bias as output node and the word-lines as input nodes. For this reason, this type of array is widely referred to as the NOR type.
The present invention provides a new NOR array architecture that uses ETOX cells that utilize substrate hot-electron programming. The new architecture allows each ETOX cell to be separately and individually programmed, as well as row or column programming. This type of SHE programming is impossible for the conventional NOR array shown in FIG. 2. The new array architecture also allows single cells to be erased as well as row or column erase. Therefore, the new array architecture can result in ETOX cell performing full EEPROM functions.